ABSTRACT -- This paper illustrates partially the implementation of the IC layout design using Tanner tools, which are capable of doing design works at the netlist and mask layout levels for the 8051 High Speed Microcontroller using. This paper shows mask layout design technique. EDIF netlist files are used by SPR ( Standard Cell Place and Route) and BPR (Block Place and Route) to place and route a design. The chip was fabricated using Alcatel Microelectronics'0.5 micron CMOS technology via EUROPRACTICE service.