ABSTRACT -- In this paper, we propose a high-speed multiplier-free realization using ROM's to store the results of coefficients scalings in combination with higher signal rate and pipelined operations. By varying some parameters, the proposed structure provides various combinations of hardware and clock speed (or throughput). An example is given comparing the proposed realization with the distributed arithmetic (DA) realization. Results show that with proper choices of the parameters the proposed structure achieves a faster processing speed with less hardware, as compared to the DA realization.

KEYWORDS -- IIR filter, multiplier-free realization, pipelined realization